1. Field of the Invention
The present invention is in the field of integrated switching power circuits. The present invention is further in the field of switching power converters. The present invention further relates to the field of high frequency drivers of inductive loads. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
Modern electronic applications require power management devices that supply power to integrated circuits or more generally to complex loads. In general, power switching converters are becoming more and more important for their compact size, cost and efficiency. In particular the size of the power converters is related to the values of the passive components utilized and that, in its turn, is directly linked to the operating switching frequency.
In order to operate switching power converters at high frequencies with acceptable efficiency, the switching transitions of the power devices have to be very fast. Fast switching, when combined with high load currents, poses several challenges. In particular the interconnections of the power devices to the positive and negative terminals of the input power source are generally associated with parasitic resistances and inductances.
As mentioned, the high frequency switching of the power converters is meant to reduce the size of the main output inductor and filter capacitors. However when the value of the main inductor approaches the value of the parasitic inductances present in the circuit, the transfer of energy that occurs at every transition becomes very critical affecting negatively the efficiency and reliability of the circuit.
In particular if the operation of a buck power converter is analyzed, one can note that when the high side power device is on, if a parasitic inductance is present between the switch and the positive terminal of the power source, a small but not insignificant amount of energy gets stored in the parasitic inductance. This energy is proportional to the square of the main inductor current that is flowing in the high side power device. The amplitude of this current is typically very close to the load current.
When the high side power device turns off, the energy stored in the parasitic inductance generates a fast and temporary overvoltage at the node of the high side power device terminal. The amplitude of this overvoltage is determined by the equation:V=L di/dt From the above equation it is evident that the value of the parasitic inductance, the rate of change of the current (speed of the switching and capacitance associated with the node), and the load current have a direct impact on the overvoltage occurring across the high side switch at its turn off.
The load current establishes the energy stored in the inductor before the turn off of the power device according to the equation:E=½Li2 The higher the energy that has to be released, the higher the amplitude of the potential voltage spike at the power source interconnection.
This overvoltage can pose serious reliability problems and potentially catastrophic damage to the integrated circuit. Higher voltage devices could be used to make the circuit more robust to withstand the voltage spikes but generally that is not the preferred solution because of increased manufacturing costs and lower high frequency performances. It is therefore very important to limit or clamp as much as possible this overvoltage events.
The most common solution is to use a capacitor as shown in FIG. 1. The capacitor C2 is placed between the nodes 1 and 2. The lumped parasitic inductors L2 and L3 include the inductance of the metal interconnections in the integrated circuit, of the connections of the integrated circuit to the external world (bonding wire, bumps or metallic pillars), and of the circuit board traces. The combined inductances can typically be in the order of a few nH. The nodes 1 and 2 characterize for simplicity the nodes of the integrated circuit power pads therefore C2 is placed between the positive and the negative integrated circuit power terminals when integrated.
The capacitor C2 is charged when the transistor M1 is turned off and provides current to the load and to the reverse recovery charge of the low side transistor M2 intrinsic body diode when M1 is turned back on. Therefore the capacitor C2 is charged with the excess energy present in L2 in one switching phase and is discharged in the opposite switching phase. The value of the capacitor C2 is dependent on the power converter load current and it should be sized for the maximum load current and the maximum overvoltage that the transistor M1 can withstand without any failure.
If the current load is in the order of a few amperes, the parasitic inductance is a few nH and the switching occurs very fast, the value of the capacitor C2 can be too high to be cost effectively integrated in the chip. These considerations force the use of external capacitors placed very closely to the power distribution rail pads in order to minimize the associated parasitic inductances. Thus the manufacturing costs can become excessive to justify the utilization of high frequency power converters.
Other methods to limit the parasitic inductive overvoltage include the utilization of clamps like the one described in Cuomo et al. (U.S. Pat. No. 4,958,121) where a zener diode limits the voltage, at the drain and source terminals of a switching power device, at a desired voltage, but when the main switching inductance is of the same order of magnitude of the parasitic one, this method introduces very negative effects.
Another major limitation to the integration of very high frequency power converters is the control of the shoot-through current in the power stage. The shoot-through current is also called cross-conduction current and it refers to the phenomenon that occurs when both power devices are conducting simultaneously for a very short time of the period. In such event the possible current in the power transistors is not controlled, it can be very high, it can damage or degrade the power devices and it represents extra power dissipated in the chip, adversely affecting the overall efficiency of the power converter.
The most common solution to prevent cross-conduction current is to utilize anti cross-conduction circuits in the driver circuit as shown in FIG. 2. The depicted circuit guarantees that, when a switching transition is requested, the first occurrence is the turning off of the transistor that was on. Only after the voltage change of the gate of the device turning off is sensed, the turning on of the other power device is allowed and commanded. This circuit is very effective in assuring that the Vgs of the power devices are not above threshold simultaneously, but it introduces a propagation delay in the driver due to the number of logic gates that the driving signal has to travel through.
This driver propagation delay may not be acceptable in very high frequency power converters because the duty cycle in extreme conditions of Vout and Vin may impose to the control loop to react within very few ns. Many other schemes are used in the industry, like the one described in Audi (U.S. Pat. No. 7,187,226). One of the most common means is the optimization of break before make timing. But all these schemes are either not safe enough to preventing cross-conduction current in the power devices or they introduce transition losses that affect the overall power converter efficiency.
It is therefore a purpose of the present invention to describe a novel structure of overvoltage suppression circuit that guarantees fast power switching transitions without causing cross-conduction current in the power output stage of switching power converters, while maintaining low manufacturing costs and high conversion efficiency.